library verilog;
use verilog.vl_types.all;
entity TopLevel74181 is
    port(
        S               : in     vl_logic_vector(3 downto 0);
        A               : in     vl_logic_vector(3 downto 0);
        B               : in     vl_logic_vector(3 downto 0);
        M               : in     vl_logic;
        CNb             : in     vl_logic;
        F               : out    vl_logic_vector(3 downto 0);
        X               : out    vl_logic;
        Y               : out    vl_logic;
        CN4b            : out    vl_logic;
        AEB             : out    vl_logic
    );
end TopLevel74181;
